The present invention relates to a photolithography process for a plurality of production lots of semiconductor wafers. In particular, the present invention relates to a photolithography process for use in a photolithography system compensated based upon calibrating parameter values that are calculated by precedently processing some sample wafers.
A semiconductor device with a desired circuit is manufactured by photolithography processing (masking, exposing, and developing) a semiconductor wafer, repeatedly, with predetermined photoresists. Such photolithography processes require a more exact control for overlapping the subsequent photoresists, as increasing the density of circuits integrated into the semiconductor wafers. In particular, in case where the manufacturing process of the semiconductor wafer needs many photolithography processes, it is critical to precisely align each of subsequent photoresists patterns with the preformed pattern on the semiconductor wafer, in order to achieve a high productivity of large-scale integrated semiconductor devices. Therefore, the photolithography system should be properly maintained to precisely align each of the photoresist patterns with the preformed pattern on the semiconductor wafer, whenever the photolithography system is utilized.
By the way, the photolithography system is a highly organized and sophisticated system comprising a plurality of components (or subsystems) such as a focus subsystem and a stage subsystem. Therefore, in order to achieve a precise alignment of the photoresist patterns one another, the photolithography system should be compensated by adjusting several components properly and simultaneously. For example, a light source and/or a stage are vertically adjusted so that the distance between the light source and the stage is a focal length for obtaining a sharp image of the photoresist pattern on the semiconductor wafer, or the stage is controlled so that each of lateral displacements of the stage corresponds to a pitch between devices on a wafer. Thus, each of the components of the photolithography system has parameters to be adjusted for the precise alignment. Further, since such parameters generally deviate from their proper values as the time goes by, they should be calibrated to their proper values for maintaining the photolithography system so as to achieve the precise alignment. One solution for the precise alignment is well known as a precedent process. In the precedent process, firstly, some sample wafers in a production lot are picked and actually processed using the photolithography system prior to processing the other wafers, for obtaining the proper parameter values of the photolithography system. Then, the photolithography system is compensated based upon the proper parameter values to process the other wafers. In the present specification, a series of those processes and the sample wafers are referred to hereinafter as a xe2x80x9cprecedent processxe2x80x9d and xe2x80x9cprecedently processed sample wafersxe2x80x9d, respectively.
As described above, since the photolithography system is a highly organized system comprising many components (subsystems), the proper parameter values for achieving the precise alignment are co-relating to one another. Also, the proper parameter values depend upon the configurations and dimensions of the devices and/or wafers to be processed, including the height of the alignment mark of the device and the lateral device pitch on the wafer as indicated above. Therefore, the precedent process for achieving the precise alignment may be preferably conducted using the same photolithography system as well as the same type of sample wafers as ones in an actual production lot.
However, even where the precedent process is conducted using the same photolithography system and the same type of sample wafers as actual ones, as the times goes by, the actual parameter values are deviated or varied from the proper ones to be obsolete, as described above. Therefore, the parameter values should be calibrated to the proper parameter ones for the precise alignment, accordingly.
Referring to FIGS. 5 and 6, the details of a conventional photolithography process are described hereinafter. As shown in FIG. 5, in step 101, any one of the wafers in the production lot is picked and precedently processed to calculate the calibrating values which are deviation values from the proper parameter values of the photolithography system, that is referred to simply as the xe2x80x9ccalibrating valuesxe2x80x9d. In step 102, the mother production lot from which the wafer is sampled is processed with the photolithography system based upon the calculated calibrating values. In step 103, the sample wafer used for the precedent process is simply destroyed or recovered as it used to be before the sample wafer is precedently processed. According to the present invention, the recovering process is referred to as a xe2x80x9crecovery processxe2x80x9d, hereinafter. To improve the productivity, the sample wafer is preferably recovered. However, when the sample wafer is recovered and brought back to the mother production lot, it is necessary to await the sample wafer being recovered, which takes approximately 6 through 12 hours, and then to restart the subsequent processes for the mother production lot.
Contrary to this, an another approach is suggested that the recovered samples are dropped out from (not brought back to) the mother production lot, which are referred to as xe2x80x9coff-wafersxe2x80x9d, but such off-wafers are gathered to form a new production lot to be processed. However, according to this approach, the manufacturing process of the semiconductor wafers comprises more photolithography processes each requiring the precedent process, more off-wafers are produced and, eventually, more precedent processes are necessary, inconveniently resulting in the low productivity. In step 104, any of wafers sampled from the lot processed by the photolithography system are tested or inspected (spot-checked). Thus, a series of photolithography process is completed.
An another conventional photolithography process improving the aforementioned process is illustrated in FIG. 6. In this process, only the very first production lot is processed as described above in order to obtain the calibrating values for compensating the photolithography system. Then, in step 111, for the second and following production lots, the photolithography system is compensated based upon the calibrating values calculated when the prior production lot has been processed, rather than based upon the calibrating values calculated by precedently processing sampled wafers. In step 112, the second or following production lot is processed with the photolithography system compensated based upon the calibrating value calculated during processing the prior production lot. Then, in step 113, a new calibrating value is calculated for the next production lot. In other words, in steps 111 through 113, the new calibrating values are calculated and fed back into the next photolithography process. Thus, according to this conventional photolithography process, the calibrating values are updated always as a production lot is processed, and it is not necessary to await the wafers recovered nor to abandon the off-wafers. This approach is particularly advantageous for devices, which are often manufactured (large numbers of devices or production lots), such as DRAMs since the calibrating values are often updated.
On contrary to this, if this approach is used for devices, which are seldom manufactured (small numbers of devices or production lots), such as ASICs, this would cause a problem. That is, after the calibrating parameter values of the photolithography system is updated for the next production lot, a substantial time period, for example, a several weeks may pass until the calibrating parameter values is actually xe2x80x9cfed backxe2x80x9d into the next production lot. As described above, the actual parameter values generally deviate from the proper ones for the precise alignment of the photoresist patterns, as the time goes by. Therefore, such calibrating parameter values are too obsolete to feed back into the next production lot. In fact, the calibrating parameter values will be obsolete and should be evaluated again in a different way, after a predetermined time period (for example 24 hours) has passed, in which the calibrating parameter values secure to compensate the system of the photolithography system.
Therefore, the present invention addresses the problems as aforementioned and the first object of the present invention is to provide a photolithography process for use in the photolithography system compensated based upon the calibrating parameter values which are fresh and not obsolete, by determining whether a predetermined time period expires from the time when the calibrating parameter values are obtained until the time when an actual production lot is processed, and by updating the calibrating parameter values if they are obsolete.
The second object of the present invention is to provide a photolithography process for use in the photolithography system compensated based upon the calibrating parameter values, in which the alignment accuracy of photoresists can be selectively adjusted by arbitrarily choosing the predetermined time period.
The third object of the present invention is to provide a photolithography process for use in the photolithography system compensated based upon the calibrating parameter values, in which the mother production lot are processed without a hitch, i.e., without a need for awaiting the precedently processed wafers recovered.
The fourth object of the present invention is to provide a photolithography process for use in the photolithography system compensated based upon the calibrating parameter values, in which off-wafers are minimized in number to achieve the maximum productivity.
The photolithography process of first aspect according to the present invention, in which a production lot having a plurality of semiconductor wafers is processed with a photolithography system compensated based upon calibrating parameter values obtained in a precedent process, comprises steps of: a) precedently processing at least one of first lot wafers sampled from a first production lot so as to obtaining first calibrating parameter values; b) calculating a time period (Tm) after obtaining the first calibrating parameter values until processing an m-th production lot (m is a natural number of more than 2); c-1) if the time period (Tm) does not exceed a predetermined time period (Ts), processing the m-th production lot with the photolithography system compensated based upon the first calibrating parameter values; and c-2) if the time period (Tm) exceeds the predetermined time period (Ts), keeping at least one of m-th lot wafers sampled from the m-th production lot, precedently processing the first lot wafers again which is recovered so as to obtain m-th calibrating parameter values, and processing the m-th production lot with the photolithography system compensated based upon the m-th calibrating parameter values.
In the photolithography process according to the present invention, if the time period (Tm) exceeds the predetermined time period (Ts), the m-th production lot is processed with the photolithography system compensated based upon the m-th calibrating parameter values within the predetermined time period (Ts) after obtaining the m-th calibrating parameter values.
In the photolithography process according to the present invention, if the time period (Tm) exceeds the predetermined time period (Ts), further comprises steps of:
twice recovering the first lot wafers; and incorporating the first lot wafers into the m-th production lot.
The photolithography process according to the present invention, further comprises a step of: conducting a sampling inspection for the m-th production lot by sampling at least one of the former first lot samples which are incorporated into the m-th production lot.
The photolithography process of second aspect according to the present invention, further comprises steps of: d) calculating a time period (Tn) after obtaining the m-th calibrating parameter values until processing an n-th production lot (n is a natural number of more than 3); e-1) if the time period (Tn) does not exceed the predetermined time period (Ts), processing the n-th production lot with the photolithography system compensated based upon the m-th calibrating parameter values; and e-2) if the time period (Tn) exceeds a predetermined time period (Ts), keeping at least one of n-th lot wafers sampled from the n-th production lot, precedently processing the m-th lot wafers so as to obtain n-th calibrating parameter values, and processing the n-th production lot with the photolithography system compensated based upon the n-th calibrating parameter values.
In the photolithography process according to the present invention, if the time period (Tn) exceeds the predetermined time period (Ts), the n-th production lot is processed with the photolithography system compensated based upon the n-th calibrating parameter values within the predetermined time period (Ts) after obtaining the n-th calibrating parameter values.
In the photolithography process according to the present invention, if the time period (Tn) exceeds the predetermined time period (Ts), further comprises steps of: recovering the m-th lot wafers; and incorporating the m-th lot wafers into the n-th production lot.
The photolithography process according to the present invention, further comprises a step of: conducting a sampling inspection for the n-th production lot by sampling at least one of the former m-th lot samples which are incorporated into the n-th production lot.
A photolithography process of third aspect according to the present invention, in which a production lot having a plurality of semiconductor wafers is processed with a photolithography system compensated based upon calibrating parameter values obtained in a precedent process, comprises steps of: a) processing an n-th production lot (n is a natural number of more than 3) with a photolithography system compensated based upon n-th calibrating parameter values, which are obtained by precedently processing an m-th production lot (m is a natural number of more than 2) b) keeping at least one of n-th lot wafers sampled from the n-th production lot; c) calculating a time period (Tk) after obtaining the n-th calibrating parameter values until processing a k-th production lot (k is a natural number of more than 4); d-1) if the time period (Tk) does not exceed a predetermined time period (Ts), processing the k-th production lot with the photolithography system compensated based upon the n-th calibrating parameter values; and c-2 ) if the time period (Tk) exceeds the predetermined time period (Ts), keeping at least one of k-th lot wafers sampled from the k-th production lot, precedently processing the n-th lot wafers to obtain k-th calibrating parameter values, and processing the k-th production lot with the photolithography system compensated based upon the k-th calibrating parameter values.
In the photolithography process according to the present invention, if the time period (Tk) exceeds the predetermined time period (Ts), wherein the k-th production lot is processed with the photolithography system compensated based upon the k-th calibrating parameter values within the predetermined time period (Ts) after obtaining the k-th calibrating parameter values.
In the photolithography process according to the present invention, if the time period (Tk) exceeds the predetermined time period (Ts), further comprises steps of: recovering the n-th lot wafers; and incorporating the n-th lot wafers into the k-th production lot.
The photolithography process according to the present invention further comprises a step of: conducting a sampling inspection for the k-th production lot by sampling at least one of the former n-th lot samples which are incorporated into the k-th production lot.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.